Mechanical stress control in the channel regions of metal-oxide semiconductor field-effect transistors (MOSFETs) enables overcoming the limitations incurred in the scaling down of devices.
U.S. Pat. No. 6,284,610 B1 to Cha et al. describes a poly layer to reduce stress.
U.S. Pat. No. 6,281,532 B1 to Doyle et al. describes processes to change the localized stress.
U.S. Pat. No. 5,562,770 to Chen et al. describes a process for global stress modification by forming layers or removing layers from over a substrate.
U.S. Pat. No. 5,834,363 to Masanori describes a method for global stress modification by forming layers from over a substrate.
The J. Welser et al. Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs, IEDM Tech. Dig., pp. 373–376, 1994 article discloses measurements of the strain dependence of the electron mobility enhancements in n-MOSFETs employing tensilely-strained Si channels.
The K. Rim et al. Strained Si NMOSFET's for High Performance CMOS Technology, VLSI Tech., pp. 59 and 60, 2001 article describes performance enhancements in strained Si NMOSFET's at Leff<70 nm.
The F. Ootsuka et al. A Highly Dense, High-Performance 130 nm node CMOS Technology for Large Scale System-on-a-Chip Applications, IEDM Tech. Dig., pp. 575–578, 2000 article describes a 130 nm node CMOS technology with a self-aligned contact system.
The Shinya Ito et al. Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design, IEDM Tech, Dig.; pp. 247–250, 2000 article describes process-induced mechanical stress affecting the performance of short-channel CMOSFET's.
The A. Shimizu et al. Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement, IEDM Tech. Dig., pp. 433–436, 2001 article describes a “local mechanical-stress control” (LMC) technique used to enhance the CMOS current drivability.